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Helpful ReplyTrying to Understand Rocket Lake 20 CPU Lanes Distribution

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frankd3
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2021/05/02 11:32:51 (permalink)
Hi,
Reading the manual tells me that PCIe slot PE1 is x16 and shares it's 20 Gen4 lanes with PE2 and M1 (M.2 slot). If I put a card in PE2 then both PE1 and PE2 reduce to x8. Fine. I then assume that M1 is still x4.
I will not be using the PE2 slot for anything so that means that PE1 stays x16 and M1 should be x4.
 
But I want to put another NVMe drive in M3. Where does M3 get it's lanes? I keep rereading and I can't find it. Is it possible that M3 is not Gen4 like M1?
If it's Gen3 then I'm confused. Are there both Gen4 and Gen3 at the same time?
 
Please help me understand. I want to make sure I don't reduce x16 at PE1.
 
Thank you.
 
Edit:  After further research I found that the M1 and M3 slots are both x4 and the M1 is the only one labeled Gen4. Also my question about Gen3 was stupid. There is only Gen4 with the Rocket Lake.
Fortunately ASUS includes a PCIe chart in their manuals and I learned in all their Z590 models that if you use 2 M.2 slots (both labeled Gen4) at x4 it only leaves x8 for PE1 - the graphics card.
So now I have to decide which is more important.
post edited by frankd3 - 2021/05/02 13:57:10
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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/02 14:52:24 (permalink) ☄ Helpfulby frankd3 2021/05/03 04:38:23
Only the first M.2 slot is Gen 4, direct from the CPU (assuming you don't use pci-e slot 2). That gives 20x pci-e Gen 4 lanes. There are 8 lanes allotted to the chipset that are basically Gen 3 pci-e under the hood, but they call it something else. If you use Pcie slot 1 at 16x and m.2-1 at 4x, than the rest of the m.2 slots are sharing a gen-3 speed 8 lanes with all the other devices that the chipset uses (USB, sata(?not positive on sata).

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frankd3
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 04:40:01 (permalink)
Nike_7688
Only the first M.2 slot is Gen 4, direct from the CPU (assuming you don't use pci-e slot 2). That gives 20x pci-e Gen 4 lanes. There are 8 lanes allotted to the chipset that are basically Gen 3 pci-e under the hood, but they call it something else. If you use Pcie slot 1 at 16x and m.2-1 at 4x, than the rest of the m.2 slots are sharing a gen-3 speed 8 lanes with all the other devices that the chipset uses (USB, sata(?not positive on sata).

 
That is extremely helpful. Thank you!
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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 06:31:01 (permalink)
You're welcome!
 
Sorry I was on my phone when I answered so I wasn't able to look up the specific term (called "something else" lol). The 8 lanes on the chipset are called DMI (Direct Media Interface), which links the northbridge to the southbridge. Previous chipsets were limited to 4 lanes, but the new 590 series has 8, doubling the bandwidth available. As I said though, these 8 lanes are still at PCI-e gen 3 speeds and would be shared with the rest of the chipset.
 
I had to look this up before and it was one reason I never wanted a z490 or other new chipset after my x99. My current CPU has 28 PCI-e lanes and 10900k for example only has 16. The funny part was that my motherboard doesn't have any native support for m.2 NVMe SSDs, but I was able to put in a PCI-e adapter card and run an NVMe drive that way. I could have ran several. If I went with a 10900k for example, the first 16 would be allotted to graphics (unless I reduced it to 8x) and any further drives I put in would have to share the 4 lanes of DMI with the chipset. One of the improvements with Rocket Lake and the z590 chipset that I was excited about are that you have 4 more lanes of PCI-e that are gen 4 direct cpu-attachment (the 20 lanes of gen 4), and they doubled the DMI lanes. So while the DMI lanes aren't gen 4 speeds, there should be more than plenty for any of my needs. Currently, I only have one NVMe drive and it is a gen 3 that I keep all my game installs on. I'll be keeping that one there and may at some future date buy a gen 4 drive and either migrate my OS to it or use it as a big storage drive to replace my spinning drives.

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rblaes_99
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 06:41:21 (permalink)
wait what?  If i run 2 NVME drives my GPU is dropped to 8x?  is this right?


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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 07:05:39 (permalink)
rblaes_99
wait what?  If i run 2 NVME drives my GPU is dropped to 8x?  is this right?




Not necessarily. It all depends on what you're running and how you set it up. Here's a hypothetical for you:
11900k+
GPU x16 gen 4 PCI-e slot 1
m.2 x4 gen 4 in M1 slot
m.2 in M2 slot (shares 8x DMI lanes with chipset)
m.2 in M3 slot (shares 8x DMI lanes with M2 and chipset)
 
The comment I made above about reducing to 8x was with a 10900k (or 9900k, or 8700k). They only have 16x PCIe lanes and 4 DMI lanes. If you run a 10900k on a z590 board, I think you still get the 8x DMI lanes, but you don't get 20x PCIe lanes and I don't believe anything will run at gen 4 speeds. So you can run your GPU at x16, but then all the m.2's will share the 8x DMI lanes (just like they'd share the 4x DMI lanes on a z490 platform unless you ran your GPU at 8x and allotted 8x of your CPU's direct PCIe lanes to storage).
post edited by Nike_7688 - 2021/05/03 07:07:31

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rblaes_99
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 07:47:15 (permalink)
ok got it.  I have an 11900k, my kingpin 3090 and a pair of 2tb gen4 WD black 850s....  I figured I would only get gen4 on the one m.2 and the other can bog on the chipset lanes.  


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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 15:05:15 (permalink)
so if I decide to switch over from X299 to z590 and do this following setup:
 
cpu: 11900k
mobo: z590 Dark or KP edition (if it happens)
 
gpu: 3090 KingPin
m.2: nvme gen 4 (OS Drive)
m.2: nvme gen 3 (Game Files)
 
I recently purchased a Nu Audio Pro Sound Card that uses 2 of the PCIe slots. If I install this will it make the GPU go from x16 to x8? I know the card runs at PCIe x1 gen 2

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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 15:46:41 (permalink)
I honestly don't know. I would think that you would need to go to x8 on the gpu, and x4 x4 on the next two pci-e slots, but I am completely guessing there. I think 4x of the 20 lanes are for storage. Idk if you can use them for other pci-e devices or not.

Also, be careful with the Dark. Maybe others can give you more information, but I don't think all the pci-e slots are functional for that kind of thing. I can't remember where I read it, but it's common to have that last slot be for some other overclocking purpose on the Dark boards.

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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 16:19:34 (permalink)
Nike_7688
I honestly don't know. I would think that you would need to go to x8 on the gpu, and x4 x4 on the next two pci-e slots, but I am completely guessing there. I think 4x of the 20 lanes are for storage. Idk if you can use them for other pci-e devices or not.

Also, be careful with the Dark. Maybe others can give you more information, but I don't think all the pci-e slots are functional for that kind of thing. I can't remember where I read it, but it's common to have that last slot be for some other overclocking purpose on the Dark boards.



worse case scenario I don't use the sound card 

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CraptacularOne
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 16:57:37 (permalink)
Nike_7688
rblaes_99
wait what?  If i run 2 NVME drives my GPU is dropped to 8x?  is this right?




Not necessarily. It all depends on what you're running and how you set it up. Here's a hypothetical for you:
11900k+
GPU x16 gen 4 PCI-e slot 1
m.2 x4 gen 4 in M1 slot
m.2 in M2 slot (shares 8x DMI lanes with chipset)
m.2 in M3 slot (shares 8x DMI lanes with M2 and chipset)
 
The comment I made above about reducing to 8x was with a 10900k (or 9900k, or 8700k). They only have 16x PCIe lanes and 4 DMI lanes. If you run a 10900k on a z590 board, I think you still get the 8x DMI lanes, but you don't get 20x PCIe lanes and I don't believe anything will run at gen 4 speeds. So you can run your GPU at x16, but then all the m.2's will share the 8x DMI lanes (just like they'd share the 4x DMI lanes on a z490 platform unless you ran your GPU at 8x and allotted 8x of your CPU's direct PCIe lanes to storage).


10th gen CPUs do not have a DMI 8x link to the chipset, they only have a 4x link regardless of you running them in a Z490 or Z590 board. Furthermore the DMI link from the CPU to the chipset is not used in any capacity to supply lanes of anything, It is merely used to communicate with the chipset. The chipset itself supplies 24 PCIe 3.0 lanes on both Z490 and Z590. This is used to feed the bottom PCIe slot, additional M.2 slots, and SATA ports. 
 
For instance on my board if I populate all 3 M.2 slots, I lose functionality of SATA 4 & 5 but my top PCIe slot is unaffected since it's PCIe lanes are drawn directly from the CPU and not the chipset. 

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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 17:07:54 (permalink)
That would make way more sense than anything I've read in articles so far lol. Where can I find that information detailed?

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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 17:31:32 (permalink)
Nike_7688
That would make way more sense than anything I've read in articles so far lol. Where can I find that information detailed?

Z490

 
Z590


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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 17:43:51 (permalink)
Ok. So the dmi is still a factor in that it is the path between the chipset and the cpu. So I was wrong to describe it as "lanes" the way I did, but it does sort of still work that way in a manner of speed. They just aren't dedicated like pci-e lanes normally are. I also didn't know if the 8x dmi bandwidth was a chipset or cpu spec and if you'd still have that with 10th Gen on a z590.

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CraptacularOne
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 18:04:07 (permalink)
Nike_7688
Ok. So the dmi is still a factor in that it is the path between the chipset and the cpu. So I was wrong to describe it as "lanes" the way I did, but it does sort of still work that way in a manner of speed. They just aren't dedicated like pci-e lanes normally are. I also didn't know if the 8x dmi bandwidth was a chipset or cpu spec and if you'd still have that with 10th Gen on a z590.

The DMI (Direct Media Interface) is just Intel's name for the link between the CPU and the chipset. Z490 supports 4x link width and Z590 8x link width. It has to be supported on both ends in order for it to operate at it's rated width. For instance my Rocket Lake CPU supports 8x DMI link width but since it's paired with a Z490 board it only has access to 4x link width. This doesn't mean that any of my devices connected to the chipset are any slower as they are still getting their full bandwidth as provided from the chipset itself. It's just a measure of how fast and how much data that can be sent directly from the chipset to the CPU itself. If for instance all my M.2 drives wanted to send as much data as they are capable of at the same time to the CPU there would be a bottleneck in how much data could be sent at the same time. However since that will never happen under any real circumstance, it simply doesn't matter as they are often addressed individually or sequentially. 

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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 18:06:34 (permalink)
Well I'm glad you got to this thread and filled in all the blanks I left (and a couple needed corrections lol). Thanks!

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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/03 18:49:15 (permalink)
Nike_7688
Well I'm glad you got to this thread and filled in all the blanks I left (and a couple needed corrections lol). Thanks!

np 

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frankd3
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 06:38:26 (permalink)
CraptacularOne
Nike_7688
Well I'm glad you got to this thread and filled in all the blanks I left (and a couple needed corrections lol). Thanks!

np 



For me too, thank you.
Your block diagram inspired me to dig for more info. I now think I have it all figured out. If anybody can tell me I'm wrong please do so. I wanted to use 2 NVMe drives but now it looks like I will only use one and the rest will be SATA.
 
I had previously downloaded the 11th Gen Core i9 Data Sheets.
I found the following info in Vol 1:
 

Then here's the table:
 

 
It seems clear to me that only one NVMe SSD at x4 can be used and keep PE1 at x16.
If I were to install another one in M3 then it would take x4 from PE1 and reduce it to x8.
I'm not interested in using PE2 for anything.
It is also apparent that M2 is connected solely to the chipset.
 
So Intel allows two NVMe drives to work at Gen4 speeds if you're willing to take lanes away from your graphics card.
I wanted to post a link to the data sheet but it was not in the usual location. Only Vol2 was there and that one is way over my head.
You can get the data sheet by searching on Intel Support for "document number 634648-001"
 
 
Again, any fault in my conclusion?
 
EDIT: Should have made clear that M3 is only connected to processor and not the chipset. Populating it will draw lanes from PE1.
Unless I'm wrong
post edited by frankd3 - 2021/05/04 06:48:19

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rblaes_99
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 07:58:07 (permalink)
^ now I'm re-confused all over again.  


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B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 08:21:47 (permalink)
frankd3
It seems clear to me that only one NVMe SSD at x4 can be used and keep PE1 at x16.
If I were to install another one in M3 then it would take x4 from PE1 and reduce it to x8.
I'm not interested in using PE2 for anything.
It is also apparent that M2 is connected solely to the chipset.

 
rblaes_99
^ now I'm re-confused all over again.  



I don't think that part is correct, frank...unless what you wrote is not exactly what you meant lol.
 
M1 is the only one that is using any of the 20x PCIe gen 4 lanes from the CPU. M2 and M3 use the chipset lanes. Here's an excerpt from the manual:
 
You can see that PM2 shares lanes with the SATA ports 0/1. So if you have something in PM2 (what we've been calling M2 in this thread), you can't have SATA devices in 0/1 (or they share???...not sure how that works exactly but on my current board, you can only use one or the other for this type of shared connection).
 
You can see that both PM2 and PM3 are x4 lanes, but they do not come from the Gen 4 PCI-e lanes the CPU provides. As CraptacularOne showed us in the diagram, these are using the 24 chipset lanes. They are at Gen 3 speeds. 
 
OK, back to Frankd3: the x16, x8/x8, x8/x4/x4 breakdown you showed is only related to the gen 4 PCI-e lanes from the CPU and generally targeting the PCI-e slots themselves. I don't think PM2 or PM3 can use any of those. They're just using the chipset. This is made clear by indicating that they cannot use Gen 4 lanes. I don't know if you can have the other PCI-e slots use the x4 gen 4 lanes intended for storage or not because they've clearly set this up so that those are used by PM1. I'm just curious if you disabled PM1, what happens. They also make it clear that PCI-e slot 3 uses the Gen 3 chipset lanes, not the gen 4 CPU lanes. So that means the normal x8/x4/x4 usage is not an option on this board, so you are limited to either x16 in pci-e slot 1 (with no PE2 slot usage) or x8 in slot 1 and x8 in slot 2. 
 
Another note there is that only PM2 slot accepts SATA M.2 drives. PM1 and PM2 only accept PCIe M.2 drives.
 
So with all that, you should still be able to do:
PE1: x16 graphics card
PE2: empty
PM1: x4 gen 4 NVMe drive
PM2: x4 gen 3 NVMe drive
PM3: x4 gen 3 NVMe drive.
Possibly also: PE3 x4 gen 3 NVMe drive in an adapter card.
 
If you put something in PE2, it will reduce both PE1 and PE2 to 8x each. Edit: It is...possible...the way they've worded the manual I can't really tel...that if you alternatively leave PE1 empty and put something in PE2, that PE2 could then be x16. *shrugs*
post edited by Nike_7688 - 2021/05/04 08:27:22

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rblaes_99
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 08:39:49 (permalink)
yea i just want one graphics cards and two nvme drives.  one nvme at gen4 speed and one at gen 3.  


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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 08:42:14 (permalink)
rblaes_99
yea i just want one graphics cards and two nvme drives.  one nvme at gen4 speed and one at gen 3.  



You should definitely be good then. you could put your gen 3 drive in PM2 or PM3. If you don't want to risk the SATA 0/1 sharing issue, just use PM3.

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#22
frankd3
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 09:28:59 (permalink)
Nike_7688
 
OK, back to Frankd3: the x16, x8/x8, x8/x4/x4 breakdown you showed is only related to the gen 4 PCI-e lanes from the CPU and generally targeting the PCI-e slots themselves. I don't think PM2 or PM3 can use any of those. They're just using the chipset. This is made clear by indicating that they cannot use Gen 4 lanes. I don't know if you can have the other PCI-e slots use the x4 gen 4 lanes intended for storage or not because they've clearly set this up so that those are used by PM1. I'm just curious if you disabled PM1, what happens. They also make it clear that PCI-e slot 3 uses the Gen 3 chipset lanes, not the gen 4 CPU lanes. So that means the normal x8/x4/x4 usage is not an option on this board, so you are limited to either x16 in pci-e slot 1 (with no PE2 slot usage) or x8 in slot 1 and x8 in slot 2. 
 
Another note there is that only PM2 slot accepts SATA M.2 drives. PM1 and PM2 only accept PCIe M.2 drives.
 
So with all that, you should still be able to do:
PE1: x16 graphics card
PE2: empty
PM1: x4 gen 4 NVMe drive
PM2: x4 gen 3 NVMe drive
PM3: x4 gen 3 NVMe drive.
Possibly also: PE3 x4 gen 3 NVMe drive in an adapter card.
 
If you put something in PE2, it will reduce both PE1 and PE2 to 8x each. Edit: It is...possible...the way they've worded the manual I can't really tel...that if you alternatively leave PE1 empty and put something in PE2, that PE2 could then be x16. *shrugs*




Nike_7688,
 
You're right! After all that research I neglected to compare Intel's spec with the manual. EVGA has changed the setup to give us the capability you mentioned. That is excellent news and thank you for correcting me.
 
According to the Intel spec (and apparently EVGA) x4 of the Gen4 x20 is dedicated to the PM1 (or M1) slot and those 4 lanes are not usable by anything else. It appears those 4 lanes would be wasted if PM1 is empty.
 
The Intel spec backs up what you speculated in your last sentence. I believe that leaving PE1 empty would allow PE2 to use 16 lanes.
 
I'm glad I didn't buy the extra sata drive.
Now I can proceed with my original plan with an NVMe drive in PM1 (Gen4 x4) for OS
and a 2nd NVMe in PM 3 (Gen 3 x4) for games.
 
I apologize for confusing people. Thank you for your patience.
#23
frankd3
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 09:41:38 (permalink)
Just so you guys know, what got me started was that CraptacularOne's block diagram did not specifically mention the PM slots being attached to the Gen3 chipset lanes. So I went looking for backup and got all twisted up
 
#24
rblaes_99
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 10:28:06 (permalink)
i will disable all sata ports first.  never use them anymore.


#25
EVGA_Lee
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 11:11:54 (permalink)
Well, this has been a fun thread.
 
Only things to note about the Z590 FTW WIFI that hasn't been covered here are:
  1. An 11th Gen CPU is needed to use PM1.  PM1 will not function with a 10th Gen CPU (PM2/PM3 still work, though).
  2. PM1 and PM3 do not share lanes.  Use one or both without affecting performance.
  3. PE2 electrically works at Gen4 x8 speeds max with an 11th Gen CPU.  Gen3 x8 max with a 10th Gen CPU.
#26
B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 11:15:07 (permalink)
EVGATech_LeeM
Well, this has been a fun thread.
 
Only things to note about the Z590 FTW WIFI that hasn't been covered here are:
  1. An 11th Gen CPU is needed to use PM1.  PM1 will not function with a 10th Gen CPU (PM2/PM3 still work, though).
  2. PM1 and PM3 do not share lanes.  Use one or both without affecting performance.
  3. PE2 electrically works at Gen4 x8 speeds max with an 11th Gen CPU.  Gen3 x8 max with a 10th Gen CPU.




Thanks, Lee!
 
P.S. Where've you been?! lol j/k
 
P.S.S. Can you check my question on the BIOS GUI (different thread) and answer that one while you're at it? 

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#27
CraptacularOne
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 12:18:59 (permalink)
rblaes_99
i will disable all sata ports first.  never use them anymore.


Not at all necessary as leaving them enabled will not affect anything. 

EVGATech_LeeM
Well, this has been a fun thread.
 
Only things to note about the Z590 FTW WIFI that hasn't been covered here are:
  1. An 11th Gen CPU is needed to use PM1.  PM1 will not function with a 10th Gen CPU (PM2/PM3 still work, though).
  2. PM1 and PM3 do not share lanes.  Use one or both without affecting performance.
  3. PE2 electrically works at Gen4 x8 speeds max with an 11th Gen CPU.  Gen3 x8 max with a 10th Gen CPU.


Yeah I meant to clarify that with the block diagrams but guess I didn't do so clearly enough. 



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#28
rblaes_99
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 13:14:04 (permalink)
so for my second NVME M.2 drive should it be in PM2 or PM3? 
 
also does anyone even RAID0 these things any longer?  It seems like doing this has become less and less ideal.  


#29
B0baganoosh
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Re: Trying to Understand Rocket Lake 20 CPU Lanes Distribution 2021/05/04 13:16:06 (permalink)
In your case, either slot is the same.

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#30
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