nznat2013
i can run all the time at 100mhz overclock on core, 1000mhz on Vram, and i set the voltage to +20. I have power limit at max 119
 
is this considered good? 

Kylearan
I think I figured out what's going on with the power balancing on these cards.  
This may have absolutely nothing to do with the current Bios issues, or perhaps it does have something to do with it, but here is what I can work out so far.
 
The Current Sense chip controls all of the power regulation between the wattage rails, including from itself.  This is called PP Source Input Power, where PP stands for Power Plane.  It is NOT "PCI Express Slot power".
 
If any power rail has a higher resistance shunt value than the Current Sense shunt, that power rail, or the one with the highest resistance, will control via its shunt, the total amount of TDP allowed with respect to that power rail's absolute maximum limit.  The easiest example here is PCI Express.  Founder's Edition cards have an absolute 79.9W cap on the PCIE slot.  eVGA seems to either have 75W or 85W cap.  The FE card will never use a value this high---at 400W TDP and 114% power limit (from 350W To 400W), the PCIE slot is around 65 to 68W.  But it's master power limit is 79W.
If the Slot has the highest shunt resistance, the total board power cap will be reached when PCIE Slot reaches its maximum allowed Vbios value.  For example, on a FE, you would probably see 160W/160W/80W in GPU-Z (this may vary depending on how the 8 pins are shunted, but you get the picture).  A 15 mOhm stacked shunt (3.75 mOhms total shunt resistance) on PCIE slot and 10 mOhms stacked shunt on all other shunts, will allow you 466 watts of GPU power before PCIE Slot reaches 79 watts, in this case.
 
The Chip Master power limit is 300 watts.  At 400W TDP, it will never pull this limit.
 
MVDDC (FBVDD) is unknown.
 
The Current Sense shunt itself is a special case.  It seems that if the current sensing shunt is a higher resistance than all other shunts (or at least the 8 pin plugs and PCIE Slot shunts!), the resistance of the Current Sense resistor is used for "Normalized TDP" and the 8 pins and PCIE slot power draw is completely rearranged, by having the 8 pin#1 rise up to its max internal TDP value (170W on FE cards), which will be the limiting factor, and reducing the power draw of 8 pin#2 and PCIE slot, in such a way so that 8 pin#1 + 8 pin#2 + PCIE will total up to 350 watts.  If your power TDP slider is at 114%, and you are pulling 400W Total Board Power in GPU-Z (even if you're drawing more via shunt mods), the "Normalized" TDP will show up as 114%, but base TDP will be around 100%.  A shunt modded card will still of course draw more power, but will be limited in TDP To the current sense shunt (Normalized TDP!) rather than the TDP of the 8 pin power plugs and PCIE slot (regular TDP!!!)
 
If the current sense shunt is equal to or lower in resistance than the 8 pins, then the 8 pins will report balanced power, and any shunt with higher resistance will get recalculated to its max limit when total board power TDP gets reached.  For example if PCIE Slot and Current Sense have a 3.5 mOhm total shunt resistance and Chip Power has a 3.75 mOhm total shunt resistance, Chip power will reach 300 watts and signal power limit throttling when total board power approaches 400 Watts in GPU-Z.
 
Obviously this makes full sense if shunt modding and trying to use shunts with slightly different resistances and wondering why your TDP% and Normalized % are not matching, but with a stock board with the normal 5 mOhm shunts, everything should be perfectly in sync and balanced.
 
Tl;dr: i have absolutely no idea what's going on with the eVGA boards and the PCIE Slot (or MVDDC) or any other limits going on.

drunknfoo
Shunt accordingly to what power draw you want and can handle.. that said stock 450w and or the strix bios works better than the beta bios for my ftw

drunknfoo
U can check my port royal score (on air, really need a block)

Kylearan
I think I figured out what's going on with the power balancing on these cards.  
This may have absolutely nothing to do with the current Bios issues, or perhaps it does have something to do with it, but here is what I can work out so far.
 
The Current Sense chip controls all of the power regulation between the wattage rails, including from itself.  This is called PP Source Input Power, where PP stands for Power Plane.  It is NOT "PCI Express Slot power".
 
If any power rail has a higher resistance shunt value than the Current Sense shunt, that power rail, or the one with the highest resistance, will control via its shunt, the total amount of TDP allowed with respect to that power rail's absolute maximum limit.  The easiest example here is PCI Express.  Founder's Edition cards have an absolute 79.9W cap on the PCIE slot.  eVGA seems to either have 75W or 85W cap.  The FE card will never use a value this high---at 400W TDP and 114% power limit (from 350W To 400W), the PCIE slot is around 65 to 68W.  But it's master power limit is 79W.
If the Slot has the highest shunt resistance, the total board power cap will be reached when PCIE Slot reaches its maximum allowed Vbios value.  For example, on a FE, you would probably see 160W/160W/80W in GPU-Z (this may vary depending on how the 8 pins are shunted, but you get the picture).  A 15 mOhm stacked shunt (3.75 mOhms total shunt resistance) on PCIE slot and 10 mOhms stacked shunt on all other shunts, will allow you 466 watts of GPU power before PCIE Slot reaches 79 watts, in this case.
 
The Chip Master power limit is 300 watts.  At 400W TDP, it will never pull this limit.
 
MVDDC (FBVDD) is unknown.
 
The Current Sense shunt itself is a special case.  It seems that if the current sensing shunt is a higher resistance than all other shunts (or at least the 8 pin plugs and PCIE Slot shunts!), the resistance of the Current Sense resistor is used for "Normalized TDP" and the 8 pins and PCIE slot power draw is completely rearranged, by having the 8 pin#1 rise up to its max internal TDP value (170W on FE cards), which will be the limiting factor, and reducing the power draw of 8 pin#2 and PCIE slot, in such a way so that 8 pin#1 + 8 pin#2 + PCIE will total up to 350 watts.  If your power TDP slider is at 114%, and you are pulling 400W Total Board Power in GPU-Z (even if you're drawing more via shunt mods), the "Normalized" TDP will show up as 114%, but base TDP will be around 100%.  A shunt modded card will still of course draw more power, but will be limited in TDP To the current sense shunt (Normalized TDP!) rather than the TDP of the 8 pin power plugs and PCIE slot (regular TDP!!!)
 
If the current sense shunt is equal to or lower in resistance than the 8 pins, then the 8 pins will report balanced power, and any shunt with higher resistance will get recalculated to its max limit when total board power TDP gets reached.  For example if PCIE Slot and Current Sense have a 3.5 mOhm total shunt resistance and Chip Power has a 3.75 mOhm total shunt resistance, Chip power will reach 300 watts and signal power limit throttling when total board power approaches 400 Watts in GPU-Z.
 
Obviously this makes full sense if shunt modding and trying to use shunts with slightly different resistances and wondering why your TDP% and Normalized % are not matching, but with a stock board with the normal 5 mOhm shunts, everything should be perfectly in sync and balanced.
 
Tl;dr: i have absolutely no idea what's going on with the eVGA boards and the PCIE Slot (or MVDDC) or any other limits going on.

drunknfoo
U can check my port royal score (on air, really need a block)

slovak_killer

Kylearan
I think I figured out what's going on with the power balancing on these cards.  
This may have absolutely nothing to do with the current Bios issues, or perhaps it does have something to do with it, but here is what I can work out so far.
 
The Current Sense chip controls all of the power regulation between the wattage rails, including from itself.  This is called PP Source Input Power, where PP stands for Power Plane.  It is NOT "PCI Express Slot power".
 
If any power rail has a higher resistance shunt value than the Current Sense shunt, that power rail, or the one with the highest resistance, will control via its shunt, the total amount of TDP allowed with respect to that power rail's absolute maximum limit.  The easiest example here is PCI Express.  Founder's Edition cards have an absolute 79.9W cap on the PCIE slot.  eVGA seems to either have 75W or 85W cap.  The FE card will never use a value this high---at 400W TDP and 114% power limit (from 350W To 400W), the PCIE slot is around 65 to 68W.  But it's master power limit is 79W.
If the Slot has the highest shunt resistance, the total board power cap will be reached when PCIE Slot reaches its maximum allowed Vbios value.  For example, on a FE, you would probably see 160W/160W/80W in GPU-Z (this may vary depending on how the 8 pins are shunted, but you get the picture).  A 15 mOhm stacked shunt (3.75 mOhms total shunt resistance) on PCIE slot and 10 mOhms stacked shunt on all other shunts, will allow you 466 watts of GPU power before PCIE Slot reaches 79 watts, in this case.
 
The Chip Master power limit is 300 watts.  At 400W TDP, it will never pull this limit.
 
MVDDC (FBVDD) is unknown.
 
The Current Sense shunt itself is a special case.  It seems that if the current sensing shunt is a higher resistance than all other shunts (or at least the 8 pin plugs and PCIE Slot shunts!), the resistance of the Current Sense resistor is used for "Normalized TDP" and the 8 pins and PCIE slot power draw is completely rearranged, by having the 8 pin#1 rise up to its max internal TDP value (170W on FE cards), which will be the limiting factor, and reducing the power draw of 8 pin#2 and PCIE slot, in such a way so that 8 pin#1 + 8 pin#2 + PCIE will total up to 350 watts.  If your power TDP slider is at 114%, and you are pulling 400W Total Board Power in GPU-Z (even if you're drawing more via shunt mods), the "Normalized" TDP will show up as 114%, but base TDP will be around 100%.  A shunt modded card will still of course draw more power, but will be limited in TDP To the current sense shunt (Normalized TDP!) rather than the TDP of the 8 pin power plugs and PCIE slot (regular TDP!!!)
 
If the current sense shunt is equal to or lower in resistance than the 8 pins, then the 8 pins will report balanced power, and any shunt with higher resistance will get recalculated to its max limit when total board power TDP gets reached.  For example if PCIE Slot and Current Sense have a 3.5 mOhm total shunt resistance and Chip Power has a 3.75 mOhm total shunt resistance, Chip power will reach 300 watts and signal power limit throttling when total board power approaches 400 Watts in GPU-Z.
 
Obviously this makes full sense if shunt modding and trying to use shunts with slightly different resistances and wondering why your TDP% and Normalized % are not matching, but with a stock board with the normal 5 mOhm shunts, everything should be perfectly in sync and balanced.
 
Tl;dr: i have absolutely no idea what's going on with the eVGA boards and the PCIE Slot (or MVDDC) or any other limits going on.

Your theory has multiple loop holes, "The Chip Master power limit is 300 watts" this statement is not true as I was able to draw multiple times above 300W.
Also this power balancing doesnt make much sense as if u input -64mhz offset on core clock, nothing in terms of power delivery specs changes but your power draw will shoot up significantly as the card is now boosting to 1043mV. I had no problem sustaining around 470-480W.