the_Scarlet_one
I thought the m.2 came off the pch instead of pulling from PCI lane 2 on the micro boards. I cannot find a definitely answer in the manual for the motherboard.
Yea, it is not very clear in the Manual.
On Z370 motherboards, the CPU and PCH are directly linked via DMI 3.0, which uses 4 lanes to provide transfer rates at up to 8 GT/s per lane. From there, the PCH allocates bandwidth to smaller PCIe slots and devices, such as M.2 Key-E, USB, audio, etc. In simplified terms, the PCH works as a hub for peripherals that are less bandwidth-intensive.
11. PCIe Slot x16/x8
PCIe x16/x8 slots are primarily for video cards. These full-length slots will provide 8 or 16 lanes of bandwidth to a full-size card, and are backwards-compatible with x8, x4, and x1-length cards.
Coffee Lake-S Socket 1151 processors have 16 PCIe lanes available for routing.
The 16 PCIe lanes are pulled from the CPU and shared with the x16 PCIe slot 2 (PE2). Lanes automatically switch from x16/x0 to x8/x8 when the motherboard detects a card in slot PE2.
12. PCIe Slot x8
PCIe x8 slots are primarily used for video cards, and share lanes from adjacent x16 slots, when populated. These full-length slots will provide 8 lanes of bandwidth to a full-size card, and are backwards-compatible with x8, x4, and x1-length cards.
This slot is limited to a maximum of 8 lanes as it shares bandwidth with the primary PCIe x16 slot 1 (PE1). This slot is primarily recommended for secondary video cards, such as the 2
nd card in a SLI configuration, or a PhysX card. 13. PCIe Slot x4 PCIe Slot x4
PCIe x4 slot PE3 uses up to 4 Gen 3 lanes from the PCH. This slot is typically used for sound cards, WiFi, USB, LAN or other peripheral cards.
Using this slot will have *NO EFFECT* on the bandwidth or throughput of the x16 slots used for SLI because this slot uses only PCH bandwidth.
PCIe Slot Breakdown
PCIe Lane Distribution (All Socket 1151 processors provide 16 lanes.)
PE1 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE2) PE2 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE1’s 16 lanes) PE3 – x4 (Gen3, x4 lanes from PCH) M.2 Slot Breakdown
M.2 Lane Distribution
M.2 Key-M (80mm) – x4 o M.2 Enable/Disable is set within the BIOS
M.2 Key-E (32mm) – x1 o M.2 Enable/Disable is set within the BIOS
This motherboard does NOT have any lane replication via PLX; all lanes are native and derived from CPU or PCH.
post edited by bcavnaugh - 2018/10/16 09:38:38