EVGA

SLI Disables M.2?

Author
ksuaviator
New Member
  • Total Posts : 82
  • Reward points : 0
  • Joined: 2018/03/09 13:52:45
  • Status: offline
  • Ribbons : 0
2019/05/03 12:19:45 (permalink)
I was reading up on the X299 Dark Manual when I came across a note that says that SLI Disables the functionality of M.2 Key-M(PM1)
 
It is listed under the Kaby Lake X lane distribution section.
 
I have a Skylake X refresh, not Kaby Lake X but the formatting of the note is confusing. I'm not sure if it applies to SLI for the X299 Dark or if it only applies to the Kaby Lake X chips.
 
Here's what I'm talking about from page 29 in the X299 Dark Manual
 
 

Attached Image(s)

#1

4 Replies Related Threads

    Sajin
    EVGA Forum Moderator
    • Total Posts : 36789
    • Reward points : 0
    • Joined: 2010/06/07 21:11:51
    • Location: Texas, USA.
    • Status: online
    • Ribbons : 194
    Re: SLI Disables M.2? 2019/05/03 12:44:40 (permalink)
    Only for kaby lake.

    Want to save 5 to 10% on your next EVGA purchase? Just click on the associates banner to save, or enter the associates code at checkout on your next purchase. If you choose to use my code I want to personally say "Thank You" for using it.
     

     
    #2
    GGTV-Jon
    FTW Member
    • Total Posts : 1784
    • Reward points : 0
    • Joined: 2017/11/25 14:11:43
    • Location: WA, USA
    • Status: offline
    • Ribbons : 17
    Re: SLI Disables M.2? 2019/05/03 20:22:26 (permalink)
    Which CPU do you actually have, a 44 lane or 28 lane Skylake-X?
     
    You should be looking at pages 27 and 28 for Skylake-X not pages 29 and 30
     
    In regards to SLI you would be using PE1 and PE4 for full 16x SLI configuration on the 44 lane Skylkake-X - neither of them have anything to do with PM1 or PM2
     
    PM1 only affects PU1 (U.2 drive port) and PM2 only affects PE6 which is an 8x port - which would only be used in a quad SLI setup
     
    Note though PE4 is only an 8x lane slot on the 28 lane 78** series Skylake-X cpu's, where it is a full 16x on the 44 lane chips
     
    Edit note - when they share CPU lanes (PM2 and PE6), when you select that device to use CPU then the shared counterpart uses PCH lanes. The only thing that actually gets shut off is the PM1 and PU1 as that is one or the other and neither has access to PCH lanes
    post edited by GGTV-Jon - 2019/05/03 20:27:07


    #3
    rjohnson11
    EVGA Forum Moderator
    • Total Posts : 71155
    • Reward points : 0
    • Joined: 2004/10/05 12:44:35
    • Location: Europe
    • Status: offline
    • Ribbons : 67
    Re: SLI Disables M.2? 2019/05/04 02:18:43 (permalink)
    I was tired of running out of resources so I decided to go with Threadripper. 

    Specs: AMD 2920X Threadripper, Corsair MP510 M.2, 64GB Corsair RGB Dominator,  ASRock X399 Taichi, Corsair 1000D, EVGA RTX 2080 Black




    #4
    rjohnson11
    EVGA Forum Moderator
    • Total Posts : 71155
    • Reward points : 0
    • Joined: 2004/10/05 12:44:35
    • Location: Europe
    • Status: offline
    • Ribbons : 67
    Re: SLI Disables M.2? 2019/05/04 04:03:50 (permalink)
    I think Intel is trying to increase the number of lanes in their newer processors. I believe we'll see more of these increases this year and next year. 

    Specs: AMD 2920X Threadripper, Corsair MP510 M.2, 64GB Corsair RGB Dominator,  ASRock X399 Taichi, Corsair 1000D, EVGA RTX 2080 Black




    #5
    Jump to:
  • Back to Mobile