Mine shows in BIOS it's detected in the PE1 as Gen4 x16 as well as in Aida 64 Extreme. Bios 2.08. I have PCIe Slots Dip Switches 2-5 set to Off.
I have two M2 drives installed. 1st and 3rd slots. Even if I disable the M2 Slots it still shows Gen4x16 in the Bios even after a Power Down.
What other PCIe Devices do you have installed?
Also in the Bios is Slot 1 set to Auto are did you select 4?
2x PCIe Gen5 x16 slots -
1x16/8, 1x81x PCIe Gen3 x4 slot (via PCH)
❑ PCIe 5.0 Support:
Low power consumption and power management features
❑ SLI and Crossfire Support:
NVIDIA® SLI® Ready, 2-Way Crossfire
❑ Additional Expansion Slots:
1x M.2 Key-M 110mm Gen4 slot from CPU
2x M.2 Key-M 110mm Gen4 slot from PCH
1x M.2 Key-E slot
1x U.2 port
12. U.2 Port (SFF-8643)
U.2, originally known as SFF-8643, is a high bandwidth connection specifically engineered for next generation SSDs. U.2 brings PCIe x4 (Gen3) NVMe performance to a 2.5” SSD form factor and provides a solution to potential heating problems that may be present in some M.2 solutions. Port function depends upon BIOS Configuration. Note: SFF-8643 ports are located on the motherboard side; SFF-8639 ports are located on the storage side.
13. M.2 Socket 3 Key-M 110mm (M.2_1, M.2_2, and M.2_3)
M.2 is an SSD form factor standard, which uses up to four PCIe lanes and utilizes up to Gen4 speeds, depending upon the device used. Most popularly paired with NVMe SSDs, this standard offers substantially faster transfer speeds and seek time than SATA interface standards. All M.2 devices are designed to connect via a card-bus style connector, secured by bolting into place, and powered by the connector – rather than a dedicated data cable and power cable.
This slot supports device lengths of 110mm, 80mm, 60mm, and 42mm.
14. PCIe Slot x16/x8*
Alder Lake-S processors have 20 PCIe lanes available for routing.
Up to x16 Gen5 PCIe lanes are pulled from the CPU and shared with the x8 PCIe slot 2 (PE2). Lanes automatically switch from x16/x0 to x8/x8 when the motherboard detects a card in slot PE2.
* Please see the description for Physical (length) vs Electrical (lanes) on Page 24.
15. PCIe Slot x8*
PCIe x16/x8 slots are primarily for video cards. These full-length slots will provide up to 8 lanes of bandwidth to a full-size card, and are backwards compatible with x8, x4, and x1 length cards.
This slot is limited to a maximum of 8 lanes because it shares bandwidth with the primary PCIe x16 slot 1 (PE1). This slot is primarily recommended for secondary video cards, such as the 2nd card in a SLI configuration, a capture card, audio card, etc.
* Please see the description for Physical (length) vs Electrical (lanes) on Page 24.
16. PCIe Slot x4*
PCIe x4 is a smaller form-factor PCIe card slot. These can be used for low-bandwidth products, such as a PCIe SSD card, capture card, audio card, etc.
This slot is limited to a maximum of x4 Gen3 CPU lanes, as it shares bandwidth with the third M.2 Key-M (PM3). This slot is primarily recommended for capture cards, audio cards, etc.
* Please see the description for Physical (length) vs Electrical (lanes) on Page 24.
* There are two numeric references for PCI-Express: one is mechanical (the physical length on the motherboard), while the second is electrical (the number of PCIe lanes available to the slot from the CPU, PCH, or both).
PCI-Express was designed to be universal; e.g. you can install x1 devices, such as sound cards or USB controllers, into an x16 slot. Similarly, some applications might only use certain parts of a device (e.g. compute apps), requiring only a single PCIe lane to accomplish its task without affecting performance. This is why there are x16 mechanical slots with an x1 electrical PCIe lane. Using the entire length of a PCIe slot is unnecessary, nor does it cause an adverse effect to use a shorter form-factor bus card in a slot that physically can hold a larger form-factor bus card.
PCIe Slot Breakdown
PCIe Lane Distribution
❑ PE1 – x16 (Gen5, x16 lanes from CPU, x8 shared with PE2)
❑ PE2 – x8 (Gen5, x8 lanes from CPU)
❑ PE3 – x4 (Gen3, x4 lanes from PCH, x4 shared with PU)