https://www.techpowerup.com/274720/tsmc-achieves-major-breakthrough-in-2-nm-manufacturing-process-risk-production-in-2023
 
The Taiwan Economic Daily claims that TSMC has achieved a major internal breakthrough for the eventual rollout of 2 nm fabrication process technology. According to the publication, this breakthrough has turned TSMC even more optimistic towards a 2023 rollout of 2 nm risk production - which is all the more impressive considering reports that TSMC will be leaving the FinFet realm for a new multi-bridge channel field effect transistor (MBCFET) architecture - itself based on the Gate-All-Around (GAA) technology. This breakthrough comes one year after TSMC put together an internal team whose aim was to pave the way for 2 nm deployment.

MBCFET expands on the GAAFET architecture by taking the Nanowire field-effect transistor and expanding it so that it becomes a Nanosheet. The main idea is to make the field-effect transistor three-dimensional. This new complementary metal oxide semiconductor transistor can improve circuit control and reduce leakage current. This design philosophy is not exclusive to TSMC - Samsung has plans to deploy a variant of this design on their 3 nm process technology. And as has been the norm, further reductions in chip fabrication scale come at hefty costs - while the development cost for 5 nm has already achieved $476M in cost, Samsung reports that their 3 nm GAA technology will cost in excess of $500M - and 2 nm, naturally, will come in even costlier than that.
 
Good to see that TSMC is aiming to stay competitive for the next few years with only Samsung as their main rival. 

Yikes,  they are a force to be reckoned with right now

2nm, that's getting pretty darn impressive now

Fascinating. I wonder when intel will finally catch up 

sparetimepc
2nm, that's getting pretty darn impressive now

There is no standard so 2nm does not actually mean anything other than a size that can only be correlated to another measurement that you probably need another party to fulfill which only differs by different entities that produced it.  For example, Intel's 14nm is barely larger than AMD's 7nm to the extent it is only about 10% smaller and although I have not verified it, I believe Intel's 10nm is smaller than AMD's 7nm.  You essentially need to look at those details in the same way you would look at the label of RTX3090 and AMD used that identical label for a slower card they produced that they call the RTX3090.

kougar

misomalu
Fascinating. I wonder when intel will finally catch up 

To be fair, Intel's 7nm density is estimated to tangibly exceed TSMC's 5nm process. But Intel won't have mass-production 7nm until 2023...  Meanwhile TSMC's 2/3nm density will give them a small lead over Intel's 7nm. 

That also assumes Intel can get it's 7nm process sorted and mass producing in a reasonable amount of time.

I want to see their eating crow response since they too are now starting to come out with "glued chips".

castrator86
But that density is the exact reason they're behind and having so many production issues. They can't get it to shrink any further; which is why we've just seen revisions of the same architecture for years on end now. They need a full re-haul and they know it but keep trying to avoid it.

It would take longer to backport EUV into 10nm than it would to just continue on for its 7nm EUV, which is what they're doing. What Intel really should have begun doing years ago was to adopt a half-node strategy. Intel is trying to eat the entire plate in one bite, while TSMC does ~3 nodes per Intel's one, biting off only what they can chew before they move on.