Alleged Intel Sapphire Rapids Xeon CPU Stripped To Expose Quad Chiplets With Up To 80 Cores | HotHardware Past leaks have suggested that Intel's upcoming 4th Gen Xeon Scalable server processors codenamed Sapphire Rapids will flex up to 56 cores and 112 threads of big iron, but maybe an even bigger flex is in store. A user who got their hands on a supposed Sapphire Rapids engineering sample did onlookers a solid by peeling away the integrated heatspreader, to reveal some interesting details. We have seen Sappire Rapids in the wild before, assuming the leaked photos that popped up in February were not fake. They showed the top and bottom of an engineering sample. That leak also came with an accompanying pin diagram, which depicted a new LGA4577-X socket.
The additional pins over LGA4189 enable some new features, some of which include DDR5 and PCI Express 5.0 support, Compute Express Link 1.1, and built-in AI acceleration using new Advanced Matrix extensions. However, none of the previous leaks exposed the parts that sit underneath the IHS. That is, until now. There's a Chinese-language video of the Sapphire Rapids chip being stripped naked, and though we can't understand most of what is being said, it is interesting to watch. After walking in the house with the chip in hand, the user puts it in a vice grip, then holds it (with a pair of pliers) over the flames of a gas stove with the IHS side down, until it fell off.
You shouldn't try this at home, but it's fun to watch from afar, with someone else's hardware. After a bit of cleanup, we are treated to some nifty die shots. The user also posted a few pictures separate from the video, like the one above. What this all reveals is an MCM (multi-chip module) design, and a 4x5 grouping. Each chiplet carries 20 Golden Cove cores, so a top-end Sapphire Rapids CPU could have as many as 80 cores in a full configuration. At least that is the case according to the photos. Whether an 80-core/160-thread Sapphire Rapids CPU ever materializes is another question, and depends in part on what Intel can do with its mesh on-chip interconnect topology.
It's more likely some (and maybe many) of the cores will be disabled. For example, an earlier leak highlighting a 56-core/128-thread Sapphire Rapids CPU noted a 3x5 layout. That works out to 15 cores per die, for 60 cores total, but one of the cores in each die was disabled, hence the 56-core design.
Intel has not said anything about cores or threads in relation to Sapphire Rapids, and in fact has said very little overall. We know the 10nm part will be featured in the Aurora exascale supercomputer at Argonne National Labs, as Intel confirmed during its 2020 Architecture Day.
The chip maker also confirmed support for DDR5 memory, and Intel documents indicate Sapphire Rapids will feature on-package HBM support as well. Official details on everything else will have to wait. Same goes for seeing how Intel's upcoming server CPUs compete against AMD's EPYC 7003 series, which helped the company more than double its data center revenue last quarter (compared to the same quarter a year ago).
It is my personal belief that AMD's upcoming new EPYC chips will still have a performance lead.
