I was reading up on the X299 Dark Manual when I came across a note that says that SLI Disables the functionality of M.2 Key-M(PM1)
 
It is listed under the Kaby Lake X lane distribution section.
 
I have a Skylake X refresh, not Kaby Lake X but the formatting of the note is confusing. I'm not sure if it applies to SLI for the X299 Dark or if it only applies to the Kaby Lake X chips.
 
Here's what I'm talking about from page 29 in the X299 Dark Manual
 
 

Which CPU do you actually have, a 44 lane or 28 lane Skylake-X?
 
You should be looking at pages 27 and 28 for Skylake-X not pages 29 and 30
 
In regards to SLI you would be using PE1 and PE4 for full 16x SLI configuration on the 44 lane Skylkake-X - neither of them have anything to do with PM1 or PM2
 
PM1 only affects PU1 (U.2 drive port) and PM2 only affects PE6 which is an 8x port - which would only be used in a quad SLI setup
 
Note though PE4 is only an 8x lane slot on the 28 lane 78** series Skylake-X cpu's, where it is a full 16x on the 44 lane chips
 
Edit note - when they share CPU lanes (PM2 and PE6), when you select that device to use CPU then the shared counterpart uses PCH lanes. The only thing that actually gets shut off is the PM1 and PU1 as that is one or the other and neither has access to PCH lanes

I think Intel is trying to increase the number of lanes in their newer processors. I believe we'll see more of these increases this year and next year.