https://ark.intel.com/products/189124/Intel-Core-i9-9900X-X-series-Processor-19-25M-Cache-up-to-4-50-GHz-
Up To 68 Platform PCIe Lanes (44 Core per CPU)
USB 2.0 Ports:
4x from Intel
® X299 PCH – 4x internal via 2 FP headers Supports transfer speeds up to 480 Mbps with full backwards compatibilityUSB 3.0 Ports:
8x from Intel
® X299 PCH – 6x external, 2x internal via 1 FP headers Supports transfer speeds up to 5Gbps with full backwards compatibilitySATA Ports: Intel
® X299 PCH Controller 6x SATA 3/6 Gbit/s (600 MB/s) data transfer rateASMedia ASM10612x SATA 3/6 Gbit/s (600 MB/s) data transfer rate Supports Windows XP, used for benching environments
Intel
® X299 PCH (Southbridge) The Platform Controller Hub (PCH) handles the role that was previously held by the South Bridge. On X299 motherboards, the CPU and PCH are directly linked via DMI 3.0, which uses 4 lanes to provide transfer rates at up to 8 GT/s per lane. From there, the PCH allocates bandwidth to smaller PCIe slots and devices, such as M.2 Key-E, USB, audio, etc. In simplified terms, the PCH works as a hub for peripherals that are less bandwidth-intensive.
PE4 – x4 (Gen3, x4 lanes from PCH)PE6 – x16 (Gen3, x8 lanes from CPU or x4 from PCH based on configuration) When populated by a video card x8 Gen3 lanes are allocated from the CPU When populated by a card using x4 or x1 lanes, and M.2 80mm slot is populated PE6 receives x4 lanes from the PCH This section introduces RAID, RAID levels, and the basics of the controller integrated into the PCH. Page 61
This motherboard does NOT have any lane replication via PLX; all lanes are native and derived from CPU or PCH. This also allows for improved backwards compatibility for Gen 2 devices.
post edited by bcavnaugh - 2019/01/06 16:42:21