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CPU PCIe Lane Count Reconciliation

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LouKur
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2019/01/06 16:20:00 (permalink)
I am trying to reconcile the 44 PCIe lanes of an i9 Intel CPU as used with the EVGA X299 Dark. Specifically, I am reconciling the 44 PCIe lanes of the Intel Core i9-9900X. At the same time I am trying to reconcile the number of X299 (PCH) PCIe lanes.
 
The X299 chipset (aka PCH) connects to the i9-9900X using 4 lanes. I see these called DMI lanes in documents for other Intel CPUs, but not for the i9-9900X. Maybe the October 2018 release of the i9-9900X is too soon for everything else to have caught up. Or maybe I have not found the right document.
 
I think the i9-9900X has 44 PCIe lanes, all available for allocation to devices like GPUs and M.2 drives, etc. I think it additionally has 4 DMI lanes, which are used to connect the X299 chipset (PCH). The CPU clearly has 4 additional (quad) memory channels for connecting to DDR4 memory.
 
Can anyone confirm these statements as being correct?:
  • The i9-9900X CPU has 44 PCIe lanes; all available for allocation to devices like GPUs, M.2 drives, sound cards, etc.
  • The i9-9900X CPU connects to the X299 chipset (aka PCH) using 4 DMI lanes, in turn allowing the PCH to provide an additional 24 PCIe lanes.
  • There are a total of 68 PCIe lanes available for assignment with an i9-9900X CPU coupled to an X299 chipset (PCH).
  • The 44 PCIe lanes from the i9-9900X CPU are the faster/capable of handling more data than the X299 PCH PCIe lanes. That is, there are:
    • 44 fast CPU supported PCIe lanes
    • 24 not-as-fast PCH supported PCIe lanes
 
Thanks in advance for your help.
 
Lou
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    bcavnaugh
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    Re: CPU PCIe Lane Count Reconciliation 2019/01/06 16:26:59 (permalink)
    https://ark.intel.com/products/189124/Intel-Core-i9-9900X-X-series-Processor-19-25M-Cache-up-to-4-50-GHz-
     
    Up To 68 Platform PCIe Lanes (44 Core per CPU)
     
    USB 2.0 Ports:
    4x from Intel ® X299 PCH – 4x internal via 2 FP headers Supports transfer speeds up to 480 Mbps with full backwards compatibility
    USB 3.0 Ports:
    8x from Intel ® X299 PCH – 6x external, 2x internal via 1 FP headers Supports transfer speeds up to 5Gbps with full backwards compatibility
    SATA Ports: Intel ® X299 PCH Controller 6x SATA 3/6 Gbit/s (600 MB/s) data transfer rate
    ASMedia ASM10612x SATA 3/6 Gbit/s (600 MB/s) data transfer rate Supports Windows XP, used for benching environments
    Intel ® X299 PCH (Southbridge)
    The Platform Controller Hub (PCH) handles the role that was previously held by the South Bridge. On X299 motherboards, the CPU and PCH are directly linked via DMI 3.0, which uses 4 lanes to provide transfer rates at up to 8 GT/s per lane. From there, the PCH allocates bandwidth to smaller PCIe slots and devices, such as M.2 Key-E, USB, audio, etc. In simplified terms, the PCH works as a hub for peripherals that are less bandwidth-intensive.
     
    PE4 – x4 (Gen3, x4 lanes from PCH)
    PE6 – x16 (Gen3, x8 lanes from CPU or x4 from PCH based on configuration)
    When populated by a video card x8 Gen3 lanes are allocated from the CPU
    When populated by a card using x4 or x1 lanes, and M.2 80mm slot is populated PE6 receives x4 lanes from the PCH
     
    This section introduces RAID, RAID levels, and the basics of the controller integrated into the PCH. Page 61
     
    This motherboard does NOT have any lane replication via PLX; all lanes are native and derived from CPU or PCH. This also allows for improved backwards compatibility for Gen 2 devices.
    post edited by bcavnaugh - 2019/01/06 16:42:21

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    Tech_JoseC
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    Re: CPU PCIe Lane Count Reconciliation 2019/01/06 16:39:01 (permalink)
    All of the Skylake X refresh chips come equipped with 44 pcie lanes and the X299 Chipset offers 24 pcie lanes. 4 of those 24 pcie lanes are available for your use via the x4 slot on the X299 Dark or via the secondary M.2 slot.
     
    The rest of the 44 pcie lanes provided by your CPU are available for use by the pcie slots on the motherboard. Slot number 5 is a x4 slot that runs off the PCH however, slot 6 can run off the CPU lanes or the PCH as well. Then both M.2 Slots can configured to use CPU lanes however, by default M.2 Slot 1 is configured to always use CPU lanes and cannot be configured to use PCH lanes.
     
    Hope this clear things up and more detailed information can be found here https://www.evga.com/supp.../files/151-SX-E299.pdf
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