EVGATech_JacobB is correct as what the Manual Shows on Page 25
M.2 and U.2 Slot Breakdown
PCI-E Lane Distribution (44 Lane SKX CPU’s)
U.2 1 – Gen3, x4 lanes from CPU (No Shared Lanes)
U.2 2 – Gen3, x4 lanes from CPU (No Shared Lanes)
M.2 Key-M (110mm) – x4 CPU lanes (No Shared Lanes) (The First M.2 Slot)
M.2 Key-M (80mm) – x4 PCH lanes (No Shared Lanes) (*)
M.2 Key-E (32mm) – x1 PCH lane (No Shared Lanes)
PCI-E Lane Distribution (28 Lane SKX CPU’s)
U.2 1 – Not functional with a 28/16 lane processor.
U.2 2 – Not functional with a 28/16 lane processor.
M.2 Key-M (110mm) – x4 CPU lanes (No Shared Lanes) (The First M.2 Slot)
M.2 Key-M (80mm) – x4 PCH lanes (No Shared Lanes) (*)
M.2 Key-E (32mm) – x1 PCH lane (No Shared Lanes)
PCI-E Lane Distribution (16 Lane KBX CPU’s)
U.2 1 – Not functional with a 28/16 lane processor.
U.2 2 – Not functional with a 28/16 lane processor.
M.2 Key-M (110mm) – x4 CPU lanes (Gen3, x4 shared with PE5) (The First M.2 Slot)
M.2 Key-M (80mm) – x4 PCH lanes (*)
M.2 Key-E (32mm) – x1 PCH lane (The First M.2 Slot) next to the First PCIe x16/8 and Called M2 Socket 3 (1) Key-M
post edited by bcavnaugh - 2018/08/17 17:46:33