Re:SR-X PCIE slot IOH BIOS mapping
2012/10/24 10:12:08
(permalink)
IOH 0 PCIe port Bifurcation Control
IOU1 - PCIe Port [x8] – x4 from this port go to PCH for SAS
PORT 1A Link Speed [GEN2] – only GEN2 supported
IOU2 - PCIe Port [x8x8] – If slot PE2 used – should be x8x8, otherwise – x16 for first top PE1 slot
PORT 2A Link Speed [GEN2] – Any speed supported
PORT 2C Link Speed [GEN2] – Any speed supported
IOU3 - PCIe Port [x8x8] – Should be always x16 – this goes to PLX upstream port (input).
PORT 3A Link Speed [GEN2] – For best speed – GEN3 supported, but can be not reliable, it’s not POR/ BIOS have no test/no tuning
PORT 3C Link Speed [GEN2]