https://www.techpowerup.com/304206/amd-navi-31-memory-cache-die-has-preparation-for-3d-vertical-cache
 
AMD possibly has a straightforward path to increasing the performance of the "Navi 31" RDNA3 GPU to power future high-end SKUs, according to semiconductor engineer Tom Wassick. The GPU's main SIMD machinery is located in the Graphics Compute Die (GCD) built on the 5 nm EUV foundry process, surrounded by six Memory Cache Dies (MCDs) built on 6 nm, which each contain GDDR6 memory controllers, and a 16 MB segment of the GPU's 96 MB Infinity Cache memory.

In microscopic observations, Wassick noticed structures on the MCD which he thinks look like an array of through-silicon vias (TSVs), of the kind used in "Zen 3" and "Zen 4" CCDs, to wire out stacked 3D Vertical Cache memory on the L3D (L3 cache die). If the theory holds up, it could be possible for AMD to increase the L3 cache segment size per MCD from 16 MB, and the GPU's overall Infinity Cache memory size. With its RDNA2 graphics architecture (RX 6000 series), AMD significantly enlarged on-die caches on its GPUs, particularly the last-level L3 cache, even giving them the special branding of "Infinity Cache," claiming that they had a big impact in lubricating the memory sub-system, letting GPUs with 256-bit memory buses compete with NVIDIA GPUs with wider 320-bit to 384-bit interfaces.
 
It will be interesting to see if AMD pursues this path.