cdc-951
So if I was to get a Intel 750, run it in the 1st slot I am assuming since it is native to the cpu pcie lanes? Also if I had 2 980 ti's cards, where should I place these 2 cards?
Will they all run at full speeds?
Will I run at Pcie 3.0 on the ssd and all cards?
lastly if not would the 2nd card run at x8 and the 1st card run at x16
Here is the slot breakdown for the Z97 Classified.
PCI-E Lane Distribution
- PE1 – x16 (x8 if PE2 is used)
PE2 – x16 (x8 if PE3 is used)
PE4 – x16 (x8 if PE6 is used)
So in essence, PE1 is fueled by the CPU and its 16 Lanes. The PLX chip will take 8 lanes from PE1 leaving it with 8, and those 8 are used for lane replication, giving 16 lanes to PE2 and PE4. Both PE2 and PE4 share their lanes as needed, (much like the 2 primary slots on the FTW board which only supports 2x SLI due to no PLX) if PE3 is populated both PE2 and PE3 will get 8 lanes, and if PE6 is used then PE4 and PE6 both get 8 lanes, PE5 is pulled form the PCH and is as such 1xc of Gen2 and is in effect completely removed form lane allocation for this discussion.
I hope that clarifies the function of the lanes and PLX.
CPU lanes are ALWAYS faster (similar bandwidth, but no PLX latency) but PLX does allow 3x and 4x SLI on boards that would otherwise have no means of supporting them. So for optimal setups it is always best and fastest to use the least PLX, however, PLX can, not always, but can argue with SSD's and other devices. So for optimal speed I would run the cards like this:
PE1 - GPU1
PE2 - empty
PE3 - empty
PE4 - GPU2
PE5 - empty
PE6 - SSD
And if this gives you problems try this configuration instead:
PE1 - SSD
PE2 - GPU1
PE3 - empty
PE4 - GPU2
PE5 - empty
PE6 - empty
Hope this helps.
**edit for formatting issue**