Clock skew is present on PCIe buses.  It is the difference in arivial times of bits to and from each PCIe device.  I believe it also applies the DDR3 memory (in that when OCing or not) the speed of the data transfere on the parallel lines can cause some of the data to arrive so much before the reset of the data that a data error occures.   I don't know all this for sure, but the adjustment may be in pico seconds. 

Ok thanks. From what I've read there is no really way to know which way to adjust it, its kind of a shot in the dark kinda thing, is this true?

Or is there some sort of master's logic that I don't know about?

Huh, I may have to try that, I can't go past 3.6 to save my life, or at least I can but it fails LinX every time, no matter the voltage. I wonder if that may be the answer...

Yea I think I need to turn off c-states and speedstep. I was hoping to leave them both on, I understand it can be done up to about 4 ghz, but I can't seem to get it to go. I think its that because it always errors out between the linx runs, where the cpu drops down for a sec.